The design for manufacturing (DFM) aims to reduce defects that occur during manufacturing, which in turn results in fewer design returns and shorter production cycles, hence lowering total product costs. Therefore, it is important to understand the source of yield issues. Most early DFM efforts concentrated on catastrophic failures such as bridging faults, or physical DFM problems. Recently, there has been an increased emphasis on identifying and analyzing parametric yield issues caused by manufacturing process variation, commonly referred to as electrical DFM (e-DFM). This is because at the technology node of 90 nm, parametric failures become significant, and at 65 nm, parametric failures become the single most critical yield-limiting factor. Existing DFM solutions focus on analyzing and detecting electrical variations mainly for digital designs. There is a need for DFM tools for analog and mixed-signal designs.
A typical analog design flow is divided into two phases: front-end phase and back-end phase. In the front-end phase, circuit designers create schematics needed to build the circuit. One of the major tasks is to place transistors with certain widths and lengths in the schematics. Transistor-level simulation tools such as SPICE simulation tools are used in this phase to verify circuit performance. To check the schematics against potential process variations, extensive simulation runs are performed.
The schematics designers then pass the design to layout designers in the back-end phase, along with some layout constraints, e.g., which transistors need to be matched, where the differential pairs are located, etc. Electrical devices and their instances in the schematics are translated into physical layout features. Using physical verification tools, layout designers then verify that the layout design complies with the design technology rules for fabrication, and that the layout matches the schematics. A parasitic extraction (PEX) may also be back-annotated to the netlist to run post-layout simulations. A netlist is a form of a circuit design. A schematic netlist is created by circuit designers while a layout netlist may be extracted from a layout using conventional LVS (layout-vs-schematic) tools.
The current design process essentially consists of a series of trial and error cycles. These cycles are highly computationally expensive, especially in the analog and mixed-signal flow, where there are multiple design corners to be covered.
Various analog devices, such as current mirrors, differential pairs, and amplifiers, are sensitive to physical layout effects. Lithography variations, for example, can have a significant impact on device dimensions such as length (L), width (W), area drain capacitance (AD), and area source capacitance (AS). Shallow trench isolation (STI) in the CMOS process may induce mechanical stresses on the transistor channel. These mechanical stresses alter the transistor channel mobility (μ) and voltage threshold (Vth). In technology nodes at 65 nm and below, geometrical and electrical parameters of a transistor are also affected by its neighboring devices in the layout design. This is sometimes referred to as proximity effects. All these physical layout effects cause deviations in electrical performance of transistors and subsequently in the circuit target specifications. If the electrical performance variations exceed electrical constraints set by, for example, front-end designers, the corresponding layout features are regarded as electrical hotspots.
To improve the manufacturing yield, electrical hotspots should be corrected before a design is taped-out. There are, however, no conventional tools for improving circuit designs that include analog designs by detecting, analyzing and correcting electrical hotspots automatically.